AB to AD - Memory Structure

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AB to AD - Memory Structure

The Allen Bradley units contain a memory structure which is partially pre-assigned in 'files' for different types of information. For example, we see N7 assigned to hold Integer values. Timers and counters also have their own pre-assigned areas. Allen Bradley also provides unassigned memory which can be set apart by the user as chunks of Integer, Timers, Counters etc. Floating point, control and other data types may be available for assigning to chunks of memory up to the limit of the particular processor's memory space. The Input and Output memory space is expanded as necessary for the modules which may be installed in the system. Even system data has its own 'file' (S2). The items within a file are addressed in standard decimal (base 10) manner.

The Automation Direct DL06 memory space is all pre-assigned. Fixed areas hold input and output information. Fixed areas are set aside for system word storage and user word storage. The addressing of the area (when referred to as words) is not delimited by type. The memory starts at 0 and works up (with some gaps) to the highest.

Some of the areas have more useful meaning as bits, not as full words. These bit areas have additional names. The addressing of each bit area begins at 0 and counts up.

Memory Referencing (Addressing)

The addressing of the words and the bit areas are in Octal (digits from 0 to 7 only). (Please refer to the DL06 manual, Chapter 4, PLC Numbering Systems). I find it less confusing to refer to any multi-digit octal number by referring to the individual numbers. Thus I pronounce 22 as “two–two” instead of “twenty-two”.

A 'V' preceeds the memory address for a word (or double word) sized location. All of the accessible memory space could be accessed as full words. Every accessible item has a 'V' reference which at least includes it (perhaps with other data).

The bit areas are, of course, addressable to the bit level using their area names (examples are: 'C' for control bit type references, 'X' for input points, 'Y' for output points). Other areas are addressable to the bit level by using instructions which support “Bit Of Word” addressing. Not all of the AD CPUs support this feature. Bit areas can be accessed as 16 bit words beginning on a 16 bit boundary (Last number is zero, the second number is even). The manual provides charts giving the 'V' memory address for these bit area sections.

A feature provided by the DirectSOFT software is alternative naming (“alias”) for the accumulated values of timers and counters and other areas. For example, V0, which holds the accumulated value for timer T0 can also be referenced as TA0. The bit memory word areas mentioned above can be more conviently addressed by prepending a 'V' to the address. For example, the 16 bits beginning at X20 can be referenced as VX20.

If the 'View - Options - Global - Display Aliases' is turned on then these references expressed as the raw 'V' memory address (for example V40401 for the word of inputs bits starting at X20) are automatically changed in the ladder to read in the 'alias' manner (for example 'VX20'). Note: even if 'Display Aliases' is turned off the addresses can still be entered in the shortened 'alias' manner. It will be displayed as the raw 'V' memory address though.

A table showing the coorespondence between Allen Bradley and Automation Direct data types is available here

Retentive status of information

By default all information in the Allen-Bradley PLC is retained through a power-off condition by a battery. Some information, during the 'pre-scan' may be cleared (for example OTE output references).

The AD PLCs would deliberately clear all information on startup if allowed. However a 'retentive' status my be set for memory areas. There are default areas which are 'retentive' when the CPU is new. These may all be changed though. It is best to review the 'retentive ranges' as a first step when starting any program, modifying them as needed. Preservation of this memory space is dependent on the battery or the Supercap (short term).

The ladder logic itself is held in EEPROM. There is also an area of 'V' memory which is mirrored into the system EEPROM. Writing to this memory area using specific commands will also mirror the information to the EEPROM. The number of times new information can be stored in the EEPROM is high but not unlimited. The EEPROM stored information is written back to the V memory area on power up. Please refer to the DL06 manual Appendix 'F' for more on this operation.

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